In today's digital age, the USB (Universal Serial Bus) interface has become the standard for connecting computers with various external devices. Whether it is transmitting data, charging devices, or connecting various peripherals, the USB interface undoubtedly provides an efficient and convenient solution for information exchange. To achieve all this, a precisely designed USB interface circuit is indispensable.

USB interface circuit principle

USB interface

The USB connector contains 4 lines, of which VBUS and GND are used to provide 5V power supply with a current of up to 500mA; and D+ and D- are used for USB data transmission. D+ and D- are a set of differential signals with a differential impedance of 90 ohms and strong anti-interference ability; if subjected to strong external interference, the corresponding levels of the two lines will increase or decrease significantly at the same time, but the direction and amplitude of the level change of the two lines are almost the same, so the voltage difference between the two can always remain relatively stable.

Extension: USB OTG (USB On-The-Go) technology adds power management (power saving) function on the basis of full compatibility with USB2.0 standard. It allows the device to operate as both a host and a peripheral, realizing data transmission between devices without a host. For example, a digital camera is directly connected to a printer. Through OTG technology, the USB ports between the two devices are connected, and the photos taken are printed out immediately.

There are 5 lines in the USB OTG interface:
2 are used to transmit data D+ and D-;
2 are power lines VBUS and GND;
1 is an ID line, which is used to identify different cable endpoints. The ID pin in the mini-A plug (i.e., A peripheral) is grounded, and the ID pin in the mini-B plug (i.e., B peripheral) is floating. When the OTG device detects the grounded ID pin, it means that the default is the A device (host), and the device that detects the floating ID pin is considered to be the B device (peripheral).

Non Return Zero Inverted Code (NRZI)

The encoding method of Non Return Zero Inverted Code is very simple, that is, the flip of the signal level represents "0", and the signal level remains "1". This encoding method can not only ensure the integrity of data transmission, but also does not require an independent clock signal to be included in the transmission process, thereby reducing the number of signal lines.

However, when a long "1" level appears in the data stream, the data stream will not be able to flip for a long time, causing the receiver to lose the synchronization signal, resulting in serious errors in the timing of reading; therefore, bit filling is required in the reverse non-return-to-zero encoding. When 6 consecutive "1" levels appear in the data stream, forced flipping (that is, automatically adding a "0" level) is required. In this way, the receiver will have a data flip at most once every seven bits in the reverse non-return-to-zero encoding, thereby ensuring the clock synchronization of the receiver. At the same time, the receiver will discard the automatically filled "0" level to ensure the correctness of the data (even if the "0" level is followed by 6 consecutive "1" levels, NRZI will still fill a "0" level);

USB data packets use reverse non-return-to-zero encoding, so no clock signal is required in the bus.

Principle of detecting low-speed/full-speed devices

USB2.0 supports three types of transmission rates: 1.5Mbps (low speed), 12Mbps (full speed), and 480Mbps (high speed); it uses the method of adding pull-up resistors on the D+ or D- signal line to identify low-speed and full-speed devices.

When there is no USB device connected to the downstream port of the host controller or hub, the pull-down resistors on the D+ and D- signal lines make the voltages of the two data lines 0V; when a low-speed device is connected, the host will detect that the D- signal line is in a high-level state because the D- signal line is connected with a 1.5K pull-up resistor; when a full-speed device is connected, the host will detect that the D+ signal line is in a high-level state because the D+ signal line is connected with a 1.5K pull-up resistor; therefore, the host can identify the device connection and transmission rate type, and the difference between full-speed devices and high-speed devices is identified through subsequent handshakes. For details, please read USB2.0 speed identification;

USB circuit design and protection

Key points of circuit filter design

The circuit filter design of the USB interface is shown in Figure 2;

L1 is a filter bead, which is used to filter out interference on the power supply. The impedance selection range of the bead is 100Ω/100MHz~1000Ω/100MHz, and the typical value is 600Ω/100MHz. The flow rate of the bead should meet the requirements of the circuit current when selecting;

L2 is a common-mode filter inductor, which is used to filter out common-mode interference on differential signals. The impedance selection range of the bead is 60Ω/100MHz~120Ω/100MHz, and the typical value is 90Ω/100MHz;

C1 and C2 are power filter capacitors, which are used to filter out interference on the power supply. The values ​​of the two capacitors C1 and C2 should differ by 100 times, with a typical value of 10uF+0.1uF; the small capacitor is used to filter out high-frequency interference on the power supply, and the large capacitor is used to filter out ripple interference on the power line;

C3 is the jumper capacitor between the interface ground and the digital ground, with a typical value of 1000pF/2KV, and the capacitance value can also be adjusted according to the actual test situation;

Key points of circuit protection design

The circuit protection design of the USB interface is shown in Figure 2;

D1, D2, and D3 can quickly discharge electrostatic interference to prevent the large amount of interference energy generated during hot plugging from impacting the circuit and causing abnormal operation of the internal circuit. D1, D2, and D3 use TVS tubes with a reverse shutdown voltage of 5V and a junction capacitance of less than 5pF;

USB2.0 PCB Layout rules

1. D+ and D- are routed in a differential manner and pass through a continuous reference plane layer to ensure impedance consistency. The differential impedance of the signal line is Z=90Ω±15%;
2. The conventional USB interface specifies a current of 500mA, but the VBUS line must be able to withstand a current of 1A (the line width is 20mil when using 1 ounce copper foil) to prevent overcurrent events;
3. The D+ and D- lines must be of equal length, with a length error of no more than 5mil; and they cannot be routed at right angles. Obtuse angles or arcs are required, and the wiring should not be changed as much as possible to ensure impedance continuity;
4. The spacing between USB signals and other CLK or differential signal lines should be >20mil;
5. ESD protection devices and common-mode inductors should be as close to the interface as possible;
6. Avoid routing USB data signal lines under or near crystal oscillators, crystals, clock signal generators, power inductors, mounting holes, magnetic devices or ICs.